The present invention relates to semiconductor devices, and more specifically, to fabrication methods and resulting structures for III-V semiconductors.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, leading to the fabrication of products with increased memory capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the power and performance of each device and tailoring to particular applications becomes increasingly significant. As demands to increase densities and reduce power consumption in transistor devices continue, new designs and fabrication techniques to achieve a reduced power consumption and enhanced efficiency are developed.